In their ongoing tussle with Moore's Law, IBM researchers this week unveiled their latest weapon to boost computing speeds - a self-assembling manufacturing process that can boost signal throughput by 35 percent in virtually all computer chips. Importantly, the new technique can be incorporated into any standard CMOS manufacturing line, without disruption or new tooling.
Taking a lesson from Mother Nature, the researchers used the natural pattern-creating process that forms seashells and snowflakes to instead make trillions of insulating vacuums around the wires that are packed next to each other inside computer chips. With the vacuum insulation, the researchers say that the electrical signals on the chips can flow 35 percent faster compared to the most advanced chips using conventional techniques.
The new technique addresses the problem known as wiring capacitance, which occurs when two conductors, such as adjacent wires on a chip, sap electrical energy from one another, generating heat and slowing the speed at which data can move through a chip. Until now, capacitance issues were addressed by pushing ever more power through chips creating, in the process, a range of other problems. While different insulating materials have been used in the past, they have tended to become tenuously fragile as chip features get smaller and smaller, and their insulating properties do not compare to those of a vacuum.
The new self-assembly technique skips the masking and light-etching process commonly used in chip manufacturing. Instead, a carbon silicate compound is poured onto the silicon wafer and baked. This compound then assembles in a directed manner, creating trillions of uniform, nano-scale holes across an entire 300 millimeter wafer. These holes are just 20 nanometers in diameter, around five times smaller than would be possible using today's most advanced lithography techniques. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires.
"This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results," said IBM's Dan Edelstein. "By moving self assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow."
The new process already has been integrated with IBM's manufacturing line in East Fishkill, New York and is expected to be fully incorporated into IBM's manufacturing lines and used in chips in 2009.
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Source: Albany NanoTech College of Nanoscale Science and Engineering
